基于FPGA的LFSR异步加解密系统  

Asynchronous LFSR encryption system based on FPGA

作　　者：潘必韬 聂小龙[1] 王祖强[1] 

机构地区：[1]山东大学信息科学与工程学院,山东济南250100

出　　处：《电子技术应用》2016年第6期56-58,共3页Application of Electronic Technique

摘　　要：线性反馈移位寄存器(LFSR)伪随机序列作为流密码的一种,具有原理清晰、不可预测性强的特点,被广泛应用于各种加解密场合。针对目前基于LFSR的加解密系统只能应用于同步工作模式的局限性,设计了一种可配置的LFSR异步加解密系统,并对其进行了基于FPGA的硬件实现。实验结果显示,其既具备LFSR序列的优秀性能,又可以实现异步加解密,具有一定的实际应用价值。As a kind of stream cipher, linear feedback shift register（LFSR） pseudo random binary sequence（PRBS） has widely applied in many encryption occasions with characters like succinct principle and strong unpredictability, to solve the limitation that encryption system based on LFSR can only work in synchronous condition, this paper proposed a asynchronous configurable LFSR encryption system, and has implemented the system in hardware based on FPGA. The experiment results shows it not only applied the LFSR sequence′s outstanding performance but also implemented asynchronous encryption. It has a certain value of practical application.

关 键 词：LFSR FPGA 异步加解密 

分 类 号：TN918[电子电信—通信与信息系统]