基于SRAM和PRAM混合主存设计  

Design of hybrid SRAM and PRAM main memory system

作　　者：姚英彪[1] 陈越佳[1] 

机构地区：[1]杭州电子科技大学通信工程学院,杭州310018

出　　处：《计算机工程与应用》2016年第13期69-75,共7页Computer Engineering and Applications

基　　金：国家自然科学基金(No.61100044);浙江省科技计划资助项目(No.2013C31100)

摘　　要：由于DRAM芯片超高的静态功耗,使得利用DRAM构建高性能计算机系统中的大容量主存遇到能耗过大问题,这激发了对新型大容量主存结构的研究。针对上述问题,设计了一种基于SRAM和PRAM的混合主存系统,该系统将SRAM作为PRAM的专用写缓存,并将改进后的LRFU算法应用到SRAM写缓存,从而在对主存系统性能影响不大的前提下,有效降低主存系统的能耗和延长PRAM的可用时间。仿真结果显示,所设计的混合存储结构的能耗-延时积(EDP)为纯DRAM存储结构的40%;此外,与纯PRAM存储结构相比,可使PRAM的写操作次数下降28.5%,与将SRAM作为Cache相比,PRAM写次数下降13%。Because of DRAM＇s ultra-high static power consumption, large capacity main memory in high performance computer system has too large energy consumption, which inspires the study of new structures of large capacity main memory. Focusing on above problems, this paper designs a hybrid main memory composed of SRAM and PRAM, and SRAM is the write buffer of PRAM. Moreover, an improved LRFU algorithm is applied to an SRAM write buffer. On the premise that the effect on the performance is not big, the energy consumption of main memory is reduced and the usable time of PRAM is extended effectively. The experimental results indicate that Energy-Delay-Product（EDP） of hybrid memory designed in the paper is 40% of pure DRAM memory. Compared with the pure PRAM structure or the structure using SRAM as Cache, PRAM write operation times are reduced 28.5% and 13%, respectively.

关 键 词：混合存储器 PRAM存储器 SRAM写缓存 低功耗 写操作次数 替换算法 

分 类 号：TP303[自动化与计算机技术—计算机系统结构]