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机构地区:[1]电子科技大学微电子与固体电子学院,成都610054
出 处:《微电子学》2016年第3期332-335,共4页Microelectronics
基 金:国家自然科学基金资助项目(61306035);中央高校基本科研业务费资助项目(ZYGX2013J031)
摘 要:基于双环路控制构建推挽结构,增强了功率管栅端的摆率,改善了无片外电容LDO的瞬态响应。此外,结合A类复合放大器特性,降低了功率管栅端阻抗,有利于提升LDO的频率稳定性。该LDO输入电压范围为2.0-3.5V,输出电压为1.8V,最大负载电流为100mA。当负载电流在1μs内从100μA跳变到100mA以及从100mA跳变到100μA时,最大下冲电压为128mV,最大上冲电压为170mV,建立时间分别为2.5μs和2.4μs,电路工作时消耗的静态电流仅为12.6μA。A capacitor-less low-dropout voltage regulator (LDO) was proposed on the base of dual-loop adjustment with push-pull stage, which had enhanced the slew-rate at the gate of the power MOSFET as well as the transient response. Apart from that, with the combination of the class-A composite amplifier, this structure lowered the impedance at the gate of the power MOSFET which benefited the frequency stability. The input voltage range of this LDO was 2.0-3.5 V with the output voltage of 1.8 V. The maximum load current was 100 mA. When the load current switched from 100 /μA to 100 mA and from 100 mA to 100 μA in 1 /μs, the maximum undershoot voltage was 128 mV while the maximum overshoot voltage was 170 mV with settling times of 2.5 /μs and 2.4 /μs, respectively. Also, the proposed I,DO consumed a quiescent current of only 12.6 /μA.
分 类 号:TN432[电子电信—微电子学与固体电子学]
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