一种38.4～43.4 GHz CMOS压控振荡器  

A 38.4-GHz to 43.4-GHz CMOS Voltage Controlled Oscillator

作　　者：王志平[1] 况立雪 陈磊[1] 池保勇[1] 

机构地区：[1]清华大学微电子学研究所,北京100084

出　　处：《微电子学》2016年第3期375-378,共4页Microelectronics

基　　金：国家自然科学基金资助项目(61331003;61222405)

摘　　要：设计了一种基于65nm CMOS工艺的交叉耦合全差分40GHz压控振荡器(VCO)。为了减小仿真结果与测试结果的差距,对电感及其连接其他元件而延长的金属线在电磁场仿真软件里重新进行了仿真。设计中应用了厚栅容抗管来增大电压的调谐范围,从而实现更高的频率覆盖范围。流片后的测试结果表明,VCO的振荡频率覆盖38.4~43.4GHz,调谐范围达到12.2%,符合基于无线局域网IEEE 802.11ad标准设计的两级下变频60GHz无线收发机对本振频率的要求。当振荡频率为39GHz时,应用该VCO的锁相环锁定在41.76GHz时测得1 MHz偏移频率处的相位噪声为-90.9dBc/Hz。芯片采用1V电源电压供电,功耗为5.7~8.6mW,核心芯片面积为(0.197×0.436)mm^2。A 40 GHz cross-coupled fully differential voltage controlled oscillator （VCO） was designed. To shorten the gap between the simulated and measured results in millimeter-wave circuits, the inductor and its extension metal line were simulated with 3D electromagnetic simulator. Thick gate varactor was utilized to widen the frequency tuning range. The VCO chip had been implemented in a 65 nm CMOS process. The measured results showed that the chip achieved a tuning range of 12. 2 % from 38.4 GHz to 43. 4 GHz, which satisfied the LO frequency requirements of the 60 GHz wireless transceiver with two stage down-conversion supporting IEEE 802.1lad. The measured phase noise of the PLL that applied the 40 GHz VCO was --90.9 dBc/Hz at 1 MHz offset when locking at 41.76 GHz. The core of the VCO consumed 5.7 mW to 8.6 mW from a 1.0 V power supply. The core die area was （0. 197×0. 436） mm2.

关 键 词：压控振荡器 CMOS 毫米波 

分 类 号：TN752[电子电信—电路与系统]