DFT与ATPG的低功耗设计原理与分析  

DFT and ATPG low power design algorithm and analysis

作　　者：丁伟 

机构地区：[1]爱特梅尔半导体科技(上海)有限公司,上海200233

出　　处：《电子设计工程》2016年第12期149-151,共3页Electronic Design Engineering

摘　　要：文中介绍了在DFT与ATPG阶段均可通过各自的方法来达到降低测试功耗的目的。以实际项目为例,阐述了在DFT过程中分步法的原理,通过此方法可显著降低在Transition测试时的捕获功耗。同时也介绍了SYNOPSYS公司推荐的降低功耗的命令,评估其在ATPG过程中对功耗的影响。在实际项目中,可综合使用这两种方法,从而达到最佳的降低功耗的目的。This paper introduces separate methods to reduce power consumption during DFT and ATPG. This paper indicates algorithm of multi-step method during DFT by taking real project as example. This method can obviously reduce capture power consumption during Transition test. Meanwhile, this paper also introduces and evaluates the command recommended by SYNOPSYS Company to reduce the power during ATPG. It＇s suggested to combine these two methods together in order to reach better power optimization.

关 键 词：分步法 覆盖率 测试向量 设计 

分 类 号：TN99[电子电信—信号与信息处理]