基于AXI4的卫星接收机DDR3多端口存储的设计  

Implantation of Satellite Receiver Multi-Port Memory Access to Single DDR3 Based on AXI4 Bus

作　　者：张宇嘉[1] 杨晓非[1] 姚行中[2] 

机构地区：[1]华中科技大学光学与电子信息学院,武汉430074 [2]第二炮兵指挥学院精确制导技术实验室,武汉430012

出　　处：《电子器件》2016年第3期617-622,共6页Chinese Journal of Electron Devices

基　　金：第二炮兵预先研究基金项目(EP121007)

摘　　要：针对卫星图像实时接收与处理系统提出的实际应用需求，采用Xilinx Virtex 6系列FPGA为平台设计了一种基于AXI4总线结构的多端口DDR3 SDRAM存储控制器。允许多模块实时对单一DDR3存储器进行访问，满足现有系统中不同模块需同时缓存各阶段卫星图像的需求。实际功能验证和ChipScope采样读写信号证明了系统的可行性与可靠性，计算得出最大传输带宽达6.0 Gbit/s、最高带宽利用率在70%～93%之间。应用AXI4总线结构，本多端口存储控制器在高速数据读写系统中具有很高的拓展应用价值。To meet the needs of real time satellite image receiving and processing system,we implanted the multi-port DDR3 SDRAM memory controller based on AXI4 bus on the platform of Xilinx Virtex 6 FPFA. Different mod-ules are available to access to the unique DDR3 memory in real time,which allows multiple processing modules to cache satellite images at different stages at the same time. Evaluated by Xilinx ChipScope software and the image processing results,feasibility and reliability of the system has been proved. Maximum bandwidth reaches 6.0 Gbit/s and maximum utilization rate up to 70%~93% according to calculation. The multi-port memory controller can be used in extended high speed read＆write applications with this standard AXI4 bus structure.

关 键 词：存储控制器 多端口 AXI4 DDR3 SDRAM FPGA 卫星图像接收处理 

分 类 号：TP334.4[自动化与计算机技术—计算机系统结构]