A 10 b 50 MS/s two-stage pipelined SAR ADC in 180 nm CMOS  

作　　者：沈易 刘术彬 朱樟明 

机构地区：[1]School of Microelectronics, Xidian University

出　　处：《Journal of Semiconductors》2016年第6期136-140,共5页半导体学报（英文版）

基　　金：supported by the National Natural Science Foundation of China(Nos.61234002,61322405,61306044,61376033);the Opening Project of Science and Technology on Reliability Physics and Application Technology of Electronic Component Laboratory(No.ZHD201302)

摘　　要：A 10-bit 50 MS/s pipelined SAR ADC is presented which pipelines a 5-bit SAR-based MDAC with a 6-bit SAR ADC.The 1-bit redundancy relaxes the requirement for the sub-ADC decision in accuracy.The SAR-based and ＂half-gain＂ MDAC reduce the power consumption and core area.The dynamic comparator and SAR control logic are applied to reduce power consumption.Implemented in 180 nm CMOS,the fabricated ADC achieves 56.04 dB SNDR and 5mW power consumption from 1.8 V power supply at 50 MS/s.A 10-bit 50 MS/s pipelined SAR ADC is presented which pipelines a 5-bit SAR-based MDAC with a 6-bit SAR ADC.The 1-bit redundancy relaxes the requirement for the sub-ADC decision in accuracy.The SAR-based and ＂half-gain＂ MDAC reduce the power consumption and core area.The dynamic comparator and SAR control logic are applied to reduce power consumption.Implemented in 180 nm CMOS,the fabricated ADC achieves 56.04 dB SNDR and 5mW power consumption from 1.8 V power supply at 50 MS/s.

关 键 词：ADC pipeline SAR MDAC 

分 类 号：TN792[电子电信—电路与系统]