An S/H circuit with parasitics optimized for IF-sampling  

作　　者：郑旭强 李福乐 王志军 李玮韬 贾雯 王志华 岳士岗 

机构地区：[1]Tsinghua National Laboratory for Information Science and Technology,Institute of Microelectronics,Tsinghua University,Beijing 100084,China [2]School of Computer Science,University of Lincoln,Lincoln,UK [3]Research Institute of Tsinghua University in Shenzhen,Shenzhen 518055,China

出　　处：《Journal of Semiconductors》2016年第6期162-166,共5页半导体学报（英文版）

基　　金：supported by the Shenzhen Project(No.JSGG20150512162029307)

摘　　要：An IF-sampling S/H is presented,which adopts a flip-around structure,bottom-plate sampling technique and improved input bootstrapped switches.To achieve high sampling linearity over a wide input frequency range,the floating well technique is utilized to optimize the input switches.Besides,techniques of transistor load linearization and layout improvement are proposed to further reduce and linearize the parasitic capacitance.The S/H circuit has been fabricated in 0.18-μm CMOS process as the front-end of a 14 bit,250 MS/s pipeline ADC.For30 MHz input,the measured SFDR/SNDR of the ADC is 94.7 dB/68.5dB,which can remain over 84.3 dB/65.4dB for input frequency up to 400 MHz.The ADC presents excellent dynamic performance at high input frequency,which is mainly attributed to the parasitics optimized S/H circuit.An IF-sampling S/H is presented,which adopts a flip-around structure,bottom-plate sampling technique and improved input bootstrapped switches.To achieve high sampling linearity over a wide input frequency range,the floating well technique is utilized to optimize the input switches.Besides,techniques of transistor load linearization and layout improvement are proposed to further reduce and linearize the parasitic capacitance.The S/H circuit has been fabricated in 0.18-μm CMOS process as the front-end of a 14 bit,250 MS/s pipeline ADC.For30 MHz input,the measured SFDR/SNDR of the ADC is 94.7 dB/68.5dB,which can remain over 84.3 dB/65.4dB for input frequency up to 400 MHz.The ADC presents excellent dynamic performance at high input frequency,which is mainly attributed to the parasitics optimized S/H circuit.

关 键 词：sample-and-hold（S/H） IF-sampling bootstrapped switches parasitics optimization high linearity 

分 类 号：TN792[电子电信—电路与系统]