倍增组值算法抑制PAPR的FPGA实现  

FPGA Realization of Multiplication Group Value Algorithm for PAPR Reduction

作　　者：何维武 谭淇文 曾康娟 

机构地区：[1]重庆金美通信有限责任公司,重庆400030

出　　处：《通信技术》2016年第7期929-936,共8页Communications Technology

摘　　要：在以前的OFDM系统PAPR研究中,提出了倍增组值算法,并做了较多理论分析,同时采用MATLAB仿真软件验证了倍增组值算法的可行性。基于此,进一步深入研究如何利用FPGA实现倍增组值算法抑制OFDM系统的峰均比,提出了在FPGA中实现峰均比抑制模块设计方案并对其加以验证。验证结果证明,提出的在FPGA中实现峰均比抑制模块设计方案简单,硬件资源占用较少,而且抑制峰均比效果较好。In the previous PAPR system OFDM research, the multiplication group value algorithm is presented, and a lot of theoretical analysis is done. Meanwhile, the MATLAB simulation software is used to verify the feasibility of the algorithm. Based on this, further research on how to use FPGA to achieve the multiplication group value algorithm to suppress the peak to average ratio of OFDM system is done, and the idea of realizing the peak to average ratio suppression module design and its verification in FPGA is proposed. The verification results indicated that the proposed realization PAPR suppression module in FPGA design is simple, with less hardware resource and fairly good suppressing PAPR.

关 键 词：正交频分复用 倍增组值算法 门限 均值模块 降峰均比模块 

分 类 号：TN929.53[电子电信—通信与信息系统]