基于FPGA的IRIG-B(DC)解码编码器设计  

Design of IRIG-B(DC)encoder and decoder based on FPGA

作　　者：李盘文[1] 高志远[1] 

机构地区：[1]中国飞行试验研究院,西安710089

出　　处：《电子测量技术》2016年第6期107-110,共4页Electronic Measurement Technology

摘　　要：针对机载测试系统以IRIG-B(DC)码作为整个系统的时间源,提出一种基于FPGA的解码编码器设计。该设计采用FPGA为主控制器,实现IRIG-B(DC)码的解码、秒脉冲生成、IRIG-B码编码等功能,当外部IRIG-B码输入中断时,可按系统时间产生IRIG-B码输出。主要阐述了IRIG-B(DC)码的格式,详细介绍了IRIG-B(DC)码解码编码器的软硬件设计,在实验室搭建测试环境对该设计进行了测试验证,结果表明该设计能够稳定可靠运行。The design of encoder and decoder based on PFGA was presented according to the IRIG-B（DC） code as the time source of the whole airborne testing system .The functions of IRIG-B（DC） decoding ,second impulse generating and IRIG-B（DC） encoding was completed by the system with FPGA controller .When the external IRIG-B （DC） code interrupted ,it was outputted according to the system time .The format of IRIG-B code was mainly stated ,meanwhile the software and hardware design of the IRIG-B（DC） encoder and decoder was introduced .The test verification was done for the design in the laboratory ,which indicated that the design can operate steadily and reliably .

关 键 词：IRIG-B(DC)码 FPGA 解码 编码 秒脉冲 

分 类 号：TN721.1[电子电信—电路与系统]