MPC8280与SDRAM之间的时序约束分析与实现  

The Temporal Constraints Analysis and Realization between the MPC8280 and SDRAM

作　　者：宁金叶[1] 罗小丽[1] 

机构地区：[1]湖南电气职业技术学院,湖南湘潭411101

出　　处：《电子技术（上海）》2016年第7期75-78,共4页Electronic Technology

摘　　要：Freescale公司的PowerQUIIC II处理器MPC8280基于G2_LE内核,片外可以连接SDRAM等多种外设,但外同步的设计方法容易造成系统时钟到达处理器与存储器的时间存在延时问题。本文研究了MPC8280与SDRAM之间的读写时序关系,分析了系统在66MHZ和100MHZ时钟条件下的时序约束限制,系统可以通过在PCB板卡上设置蛇形线等方式来解决延时问题,从而确保数据交互的准确性。The PowerQUIIC II MPC8280 based kernel G2_LE, which can connect SDRAM and other peripherals, but the method of external synchronization is easy to cause some time delay problems to the system. This paper studies the reading and writing time sequence between MPC8280 and SDRAM, and analyzes the timing constraints of two chips when the system frequency is 66 MHz and 100 MHz. The system can set the serpentine line on the PCB board or choose other ways to solve the problem of time delay, so as to ensure the accuracy of the data interaction.

关 键 词：MPC8280 SDARM 时序设计 POWERQUICC II处理器 

分 类 号：TP333.8[自动化与计算机技术—计算机系统结构]