高速图像压缩系统中DDR3控制器的实现  

Implementation of DDR3 Controller in High-Speed Image Compression System

作　　者：陈占良[1,2] 金龙旭[1] 陶宏江[1] 韩双丽[1] 

机构地区：[1]中国科学院长春光学精密机械与物理研究所,长春130033 [2]中国科学院大学,北京100049

出　　处：《电光与控制》2016年第8期85-88,共4页Electronics Optics & Control

摘　　要：数字遥感图像具有数据量大、实时处理等特点,为了满足实时图像处理系统对大容量和高带宽存储系统的需求,利用spartan6系列FPGA内嵌的DDR3控制器IP核实现对DDR3存储器的读写操作,把DDR3存储器复杂的读写时序操作简化为简单的用户接口。通过介绍DDR3存储器的特点和DDR3控制器的工作原理,并对生成的DDR3控制器进行硬件测试,证明了该控制器性能稳定;通过配置参数和接口设计把该控制器成功地应用到实时图像压缩系统中,该DDR3控制器的简单接口和灵活配置,以及DDR3存储器高带宽、大容量的特点,使DDR3存储器得到了广泛的应用。Digital remote sensing images have the features of real-time processing and huge amount of data. To meet the needs of high-capacity and high bandwidth in image processing system, DDR3 controller in spartan6 FPGA is used to realize reading/writing operation to DDR3 memory, which converts the complicated timing operation into a simple user interface. The features of DDR3 memory and the principle of DDR3 controller are introduced, and the hardware test to the DDR3 controller shows that it can work steadily. The controller is used successfully in the real-time image compression system by parameter configuration and interface design. With high-capacity and high bandwidth, DDR3 memory has found a wide application.

关 键 词：图像处理 数据存储 图像压缩系统 FPGA DDR3控制器 

分 类 号：TP75[自动化与计算机技术—检测技术与自动化装置]