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作 者:梅领亮 陈德勇[2] 郝如茜 罗颖[2] 刘霖[2]
机构地区:[1]广东正业科技股份有限公司,广东东莞523000 [2]电子科技大学光电信息学院摩米实验室,四川成都610054
出 处:《电子设计工程》2016年第14期168-171,175,共5页Electronic Design Engineering
摘 要:采用FPGA为并行处理核心,设计了基于多路FIFO的实时重构方法,实现了多通道CIS图像的实时采集、重构与传输。该方法无需任何地址操作,在保持高速重构效率的同时,减少了FPGA硬件资源消耗,降低了系统成本。现已成功应用于各种幅宽的CIS扫描系统,其中采用Camera-Link接口的1.6 m宽幅设备扫描速率高达120 MB/s,在国内尚属首例。This paper proposes and demonstrates one novel multi-channel FIFO method which can effectively realize real-time multi-channel CIS image acquisition, reconstruction and transmission. Multi-channel image data can be cached and reconstructed without any address operations. Moreover, the logic resource of FPGA and the cost of hardware system can be greatly reduced, while maintaining high efficiency of reconstruction. The method has been successfully utilized in the CIS scanning systems with various widths. Significantly, a 120 MB/s scan-rate can be obtained in a 1.6 m wide device with CameraLink interface. To our best knowledge, it's the first reported that the real-time reconstruction technique based on multi-channel FIFOs without address operation is used in wide format CIS scanner.
关 键 词:FIFO CIS FPGA 图像重构 宽幅扫描仪
分 类 号:TN29[电子电信—物理电子学]
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