一种-100dB电源抑制比的非带隙基准电压源  

A-100 dB Power Supply Rejection Ratio Non-bandgap Voltage Reference

作　　者：黄国城[1,2] 尹韬[1] 朱渊明[1,2] 许晓冬[1] 张亚朝[1,2] 杨海钢[1] 

机构地区：[1]中国科学院电子学研究所,北京100190 [2]中国科学院大学,北京100049

出　　处：《电子与信息学报》2016年第8期2122-2128,共7页Journal of Electronics & Information Technology

基　　金：国家自然科学基金(61474120);国家重点基础研究发展计划(2014CB744600)~~

摘　　要：该文提出一种非带隙基准电路，通过一个带超级源极跟随器的预调制电路提供一个稳定的电压，为基准核心电路供电。超级源极跟随器通过降低基准核心电路电源端的对地阻抗，有效提高了基准电路的电源抑制能力。该基准电路采用0．35umCMOS工艺设计并流片，测试结果表明，该电路的工作电源电压为1．8μV，静态电流约为13μA。低频处电源抑制比（PSRR）约等于-100dB，在小于1kHz频率范围内PSRR均优于-93dB。并且其片上面积仅为0．013mm2。This paper presents a non-bandgap voltage reference, which contains a pre-regulated circuit with a super source follower. The pre-regulated circuit includes a super source follower, which attenuates the impedance from the supply of the core reference circuit to ground. In this way, the pre-regulated circuit provides a relative stable voltage for the core reference circuit, improving the Power Supply Rejection Ratio （PSRR） of the output voltage of the reference. The proposed reference circuit is implemented in standard 0.35 μm CMOS process. Measured results show that the supply range is from 1.8 to 5 V and the quiescent current is only about 13 μA at room temperature. The PSRR at low frequency achieves -100 dB and the PSRR below 1 kHz is better than -93 dB. The active area of the proposed reference is only 0.013 mm2.

关 键 词：CMOS基准电路 非带隙基准电路 预调制电路 超级源极跟随器 电源抑制比 

分 类 号：TN402[电子电信—微电子学与固体电子学]