一种集成在DC-DC芯片中的电荷泵锁相环设计  

Design of A CPPLL in DC-DC Chip

作　　者：李容容[1] 

机构地区：[1]西安电子科技大学电路CAD研究所,陕西西安710071

出　　处：《电子科技》2016年第8期25-27,144,共4页Electronic Science and Technology

摘　　要：设计了一种集成在DC-DC芯片中的电荷泵锁相环。其中鉴频鉴相器（PFD）在传统的D触发器结构的基础上增加了复位延迟电路的延迟时间,减小了鉴相“死区”;电荷泵采用充放电电流对称的源极开关结构,解决了电流失配和电荷注入作用的影响;另外,设计了一种可编程的由D触发器构成的分频器电路。基于CMOS工艺,采用Cadence仿真软件对其进行仿真,结果表明该电荷泵锁相环在锁定时间、频率范围、相位抖动等方面均达到了指定的性能需求,且工作特性较好。其性能指标是：电源电压2.4 V,频率调节范围250-750 k Hz,锁定时间〈50μs,相位抖动〈30 ns。In this paper, a charge-pump phase-locked loop integrated in DC-DC chip is designed. The ‘dead- zone＇ of phase-detection is eliminated by elongating delay of the reset circuit on the basis of the traditional D flip-flop structure. The charge-pump adopts the symmetry current structure, which has a good performance in resisting current unbalance and charge injection effect. The frequency divider is programmable. Finally, Cadence simulation which is based on the CMOS technology results of the circuit show that there is a good linear characteristic for a speed locking time, a wide frequency range voltage and a low phase noise. Its performance parameters are ： power supply voltage 2. 4V, frequency range of 250 - 750 kHz, locking time is less than 50μs and the phase jitter is less than 30 ns.

关 键 词：DC-DC PLL PFD 电荷泵 可编程分频器 

分 类 号：TN86[电子电信—信息与通信工程]