用现场可编程门阵列设计IRIG-B码信号产生器  

IRIG-B signal generator designed with FPGA

作　　者：范晓东[1] 王宇[1] 陈伟[1] 

机构地区：[1]安徽四创电子股份有限公司,安徽合肥230031

出　　处：《导航定位学报》2016年第3期89-93,共5页Journal of Navigation and Positioning

摘　　要：针对电力系统传统IRIG-B码编码设备体积大、结构复杂等问题,提出一种基于FPGA的IRIG-B码信号产生器的设计方法:首先阐述方法的设计思想;然后重点描述其FPGA硬件电路设计与NiosII软件编程过程。试验结果表明,通过该方法设计IRIG-B码信号产生器可有效缩小设备体积、增强系统稳定性。To solve the problems of large volume and complex structure of the traditional IRIG-B encoder for electric system,a method of IRIG-B code signal generator based on FPGA was proposed in the paper.The idea of the method was described,and the design of the FPGA hardware circuit and the process of NiosII software programming were focused then.Experimental results showed that the method could effectively reduce the equipment size of the IRIG-B code signal generator and enhance the system stability.This method of the design had been applied in the project of BDS/GPS dual-modulus electronic time synchronization device sponsored by Electronic Information Industry Development Fund of the Ministry of Industry and Information Technology（MIIT）in which the equipment ran stably and the expected timing goals were achieved.

关 键 词：IRIG-B FPGA NIOSII BDS/GPS卫星模块 授时 

分 类 号：P228[天文地球—大地测量学与测量工程]