基于FPGA多通道多带宽多速率DDC设计  

Multi-Channel Multi-Bandwidth and Multi-Rate DDC Design Based on FPGA

作　　者：伍小保[1] 王冰[1] 陶玉龙[1] 

机构地区：[1]中国电子科技集团公司第三十八研究所,安徽合肥230088

出　　处：《雷达科学与技术》2016年第4期403-410,416,共9页Radar Science and Technology

基　　金：国家科技支撑计划项目(No.2011BAH24B05)

摘　　要：数字阵列雷达的核心内容之一是单元级回波信号中频或射频数字化后,在数字域进行幅/相加权实现接收数字波束形成,并具有灵活的波束调度和更好的抗有源干扰的性能,基于多通道数字化接收机的数字阵列模块是数字阵列雷达的关键模块。论述了数字阵列模块内部基于FPGA的多通道、多带宽、多速率数字下变频设计,包括方案设计、仿真设计和工程化设计,同时给出了设计结果,该设计方法可应用于多通道数字化接收机设计。Digital beamforming based on IF/RF frequency digitalization of the signals in individual receiver channels and the amplitude/phase weighting in digital domain is the key of digital array radar（DAR）.It is characterized by flexible beam control and excellent active-jamming suppression performance.The digital array module（DAM）based on multi-channel digital receiver is the key module of DAR.This paper introduces DAM＇s multi-channel,multi-bandwidth,multi-rate digital down-converter（DDC）based on field programmable gate array（FPGA）,including implementation method design,simulation design,and engineering design.The design results are also given.This method can utilized in the design of other multi-channel digitalization receiver.

关 键 词：多速率 多带宽 数字下变频 现场可编程门阵列 

分 类 号：TN957.5[电子电信—信号与信息处理]