Scaling dependence of memory windows and different carrier charging behaviors in Si nanocrystal nonvolatile memory devices  

作　　者：于杰 陈坤基 马忠元 张鑫鑫 江小帆 吴仰晴 黄信凡 Shunri Oda 

机构地区：[1]State Key Laboratory of Solid State Microstructures and School of Electronic Science and Engineering,Nanjing University [2]Quantum Nanoelectronics Research Center,Tokyo Institute of Technology

出　　处：《Chinese Physics B》2016年第9期518-522,共5页中国物理B（英文版）

基　　金：Project supported by the State Key Development Program for Basic Research of China(Grant No.2010CB934402);the National Natural Science Foundation of China(Grant Nos.11374153,61571221,and 61071008)

摘　　要：Based on the charge storage mode,it is important to investigate the scaling dependence of memory performance in silicon nanocrystal（Si-NC） nonvolatile memory（NVM） devices for its scaling down limit.In this work,we made eight kinds of test key cells with different gate widths and lengths by 0.13-μm node complementary metal oxide semiconductor（CMOS） technology.It is found that the memory windows of eight kinds of test key cells are almost the same of about1.64 V @ ±7 V/1 ms,which are independent of the gate area,but mainly determined by the average size（12 nm） and areal density（1.8×10^（11）/cm^2） of Si-NCs.The program/erase（P/E） speed characteristics are almost independent of gate widths and lengths.However,the erase speed is faster than the program speed of test key cells,which is due to the different charging behaviors between electrons and holes during the operation processes.Furthermore,the data retention characteristic is also independent of the gate area.Our findings are useful for further scaling down of Si-NC NVM devices to improve the performance and on-chip integration.Based on the charge storage mode,it is important to investigate the scaling dependence of memory performance in silicon nanocrystal（Si-NC） nonvolatile memory（NVM） devices for its scaling down limit.In this work,we made eight kinds of test key cells with different gate widths and lengths by 0.13-μm node complementary metal oxide semiconductor（CMOS） technology.It is found that the memory windows of eight kinds of test key cells are almost the same of about1.64 V @ ±7 V/1 ms,which are independent of the gate area,but mainly determined by the average size（12 nm） and areal density（1.8×10^（11）/cm^2） of Si-NCs.The program/erase（P/E） speed characteristics are almost independent of gate widths and lengths.However,the erase speed is faster than the program speed of test key cells,which is due to the different charging behaviors between electrons and holes during the operation processes.Furthermore,the data retention characteristic is also independent of the gate area.Our findings are useful for further scaling down of Si-NC NVM devices to improve the performance and on-chip integration.

关 键 词：silicon nanocrystals nonvolatile memory scaling dependence different charging behaviors 

分 类 号：TP333[自动化与计算机技术—计算机系统结构] S811.8[自动化与计算机技术—计算机科学与技术]