10位高速模数转换器的超低抖动时钟设计  

Design on Ultra Low Jitter Clock Circuit of 10-Bit High-Speed A/D Converter

作　　者：熊文军 徐跃峰 闵康磊 雷鸣 钟鸣 

机构地区：[1]上海航天电子技术研究所,上海201109

出　　处：《通信技术》2016年第9期1250-1254,共5页Communications Technology

摘　　要：随着通信技术的发展,通过卫星提供数据、视频的高速数据传输系统得到快速发展,模数转换器(A/D)也得到了广泛应用。然而,模数转换器在处理高频信号时,对采样时钟误差即时钟抖动(jitter)特别敏感,极小的抖动都会使信噪比(SNR)大幅下降。通过对信噪比、有效位数(ENOB)和时钟抖动之间的相互关系进行理论研究和公式推导,提出一种超低抖动的时钟电路设计方案,并对方案进行器件选型、理论计算、原理设计和测试验证。结果表明,该时钟设计方案满足高速模数转换器的使用要求。With the development of communication technology, high-speed data transmission system provided by satellite also receives speedy advance, and the analog-digital converter wide application. However, A/D is particularly sensitive to clock jitterin the processing of high-frequency signals and even little jitter would result in significant reduction of SNR（Signal-Noise Ratio）.Through the oretical study and derivation of the relationship of between SNR, the effective number of bits（ENOB） and jitter, an ultra-low clock jitter circuit design scheme is proposed. Then the device selection, theoretical calculation, design principal and test verification are done. The experiment result shows that the clock design scheme could satisfy the application requirement of high-speed A/D.

关 键 词：模数转换器 信噪比 时钟抖动 相位噪声 

分 类 号：TN792[电子电信—电路与系统]