JESD204B接口中8B10B解码电路quad_byte设计  

Quad_byte Implementation of 8B/10B Decoder in JESD204B Interface Protocol

作　　者：霍兴华[1] 姚亚峰[1] 陈朝[1] 

机构地区：[1]中国地质大学机械与电子信息学院,武汉430074

出　　处：《电子技术（上海）》2016年第8期79-83,共5页Electronic Technology

基　　金：湖北省自然科学基金面上项目(2014CFB896)资助课题

摘　　要：针对数据转换器与数字信号处理器之间数据传输速率高达12.5Gbps的高速数据接口行业新标准JESD204B协议中的解码功能要求,在8B/10B解码基础上采用四字节并行处理技术,实现了极性同步检测功能,解决了误差传递问题,并降低了电路所需工作频率,便于低成本的CMOS工艺实现。电路综合及时序仿真结果表明,该解码电路达到协议指标要求,对国内自主设计整个高速JESD204B接口电路具有一定参考价值。JESD204B is a new industry protocol for the high-speed serial interface between data converter and digital signal processor which supports the data rate up to 12.5Gbps. An 8B/10 B decoder using quad-bytes parallel processing method is designed. In addition to the correct decoding, Also completed the synchronous polarity detection, solved the error-transfer problem and decreased the theory frequency requirment of the circuit. It makes the circuit more easily to implement with low-cost CMOS process. Circult synthesization and timing simulation results show that the decoder fully meets the specification of JESD204 B protocol. This paper is valuable for the realization of the high-speed JESD204 B interface circuit independently.

关 键 词：JESD204B 8B10B解码 quad_byte 接口电路 

分 类 号：TN919.3[电子电信—通信与信息系统]