一种改进的CSA低功耗阵列乘法器的实现  

A Low Power Multiplier with Modified Carry Save Array

作　　者：徐东明[1] 卢斌[1] 

机构地区：[1]西安邮电大学通信与信息工程学院,陕西西安710061

出　　处：《微电子学与计算机》2016年第9期19-23,共5页Microelectronics & Computer

基　　金：陕西省重大科技创新项目(2015ZKC01-02)

摘　　要：以实现电能采集中所需求的低功耗、小面积的乘法器为目标,设计了一种16×16位高性能阵列改进乘法器.系统采用Booth-4编码器产生部分乘积项,通过对部分积重组后并采用改进的CSA阵列完成压缩,直接得出乘法结果.这消除了传统并行乘法器的进位加法器部分,节省了大量的晶体管,从而有效降低了系统的整体功耗.设计采用0.6μm SMIC工艺布线,利用H-spice工具仿真验证,结果表明当工作在2.0V单输入电压,150MHz输入频率时,乘法器系统功耗为8.98mW,延迟为8.76ns.The low power and small area of the multiplier is widely in the electrical energy acquisition , A High quality of 16 × 16 multiplier with Carry Save Array is designed. The modified Booth-4 algorithm is adopted to generate partial product and the design of modified CSA is introduced to compress the partial product, eliminating the propagate adder at the final stage of the conventional multipliers. Due to removal of a few transistors in the array architecture, the proposed multiplier with Carry Save Array reduces the power dissipation and the area. In the design, At the voltage of 2. 0 V, the H-spice is used to carry out the results for 0. 6μm SMIC technology which reveals the proposed design has a measured power dissipation of 8. 98 mW and that multiplication time of multiplier is 8. 76ns at a frequency of 150 MHz.

关 键 词：乘法器 低功耗 改进的CSA阵列 关键路径 Booth-4算法 

分 类 号：TP332.2[自动化与计算机技术—计算机系统结构]