一种基于UVM的混合信号验证环境  

An UVM Based Mixed-signal Verification Environment

作　　者：耿睿[1] 王小力[2] 

机构地区：[1]西安交通大学电子与信息工程学院,陕西西安710049 [2]西安交通大学理学院,陕西西安710049

出　　处：《微电子学与计算机》2016年第9期24-27,31,共5页Microelectronics & Computer

摘　　要：面向一款MCU中的Radio模块子系统,介绍了一种混合信号的验证环境,利用UVM验证方法学的灵活便捷,将主要为数字电路服务的UVM验证平台扩展到混合信号验证方面,并引入模拟断言机制,完成验证组件.验证结果表明,UVM作为一种验证方法同样适用于混合信号的验证工作,并能有效发挥其优势;同时,利用Verilog-AMS为模拟电路提供的多种建模方案加强了验证可靠性.This paper introduced a mixed-signal verification environment based on UVM, a flexible and convenient verification methodology which was usually used in digital verification task. The verification component is completed with integrating analog assertions. The verification result shows that UVM well meets the needs of mixed-signal verification and shows great performance. At the same time, multi selectable Verilog-AMS models can enhance reliability.

关 键 词：混合信号 UVM Verilog-AMS 模拟断言 可靠性 

分 类 号：TN4[电子电信—微电子学与固体电子学]