28 nm CMOS工艺下800 MS/s 10 bit DAC的设计  

Design of a 800 MS/s 10 bit DAC in 28 nm CMOS Technology

作　　者：满亮[1] 杜占坤[1] 马骁[1] 刘珂[1] 庞晓敏[1] 熊利伟 Man Liang Du Zhankun Ma Xiao Liu Ke Pang Xiaomin Xiong Liwei(Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China)

机构地区：[1]中国科学院微电子研究所,北京100029

出　　处：《半导体技术》2016年第10期730-735,共6页Semiconductor Technology

基　　金：国家科技重大专项资助项目(Y4GZ242001)

摘　　要：基于28 nm CMOS技术,采用"6+4"分段结构,设计了一款800 MS/s 10 bit三通道的电流舵型高速数模转换器(DAC)应用于视频信号处理。采用1.05 V/1.8 V的双电压域设计来保障DAC的性能,通过锁存器和电平转换的组合电路,实现了一种双电压域的数据锁存器,简化了数据维持通路;通过改进开关控制信号产生电路,降低了控制信号电压摆幅,既提高了电流源输出电阻,又降低了时钟馈通效应,且提高了DAC动态特性。DAC版图面积为1.3 mm×0.5 mm,差分150Ω负载的单通道功耗为58 m W。后仿真结果显示:典型采样率为300 MS/s时,无杂散动态范围(SFDR)为75.3 d B,总谐波失真(THD)为-71.3 d B,微分非线性(INL)小于±0.08 LSB,积分非线性(DNL)小于±0.05 LSB。Based on 28 nm CMOS technology, an 800 MS / s 10 bit 3-channel current-steering high speed digital-to-analog converter（ DAC） applied to video signal process was presented with ＂6 ＋4 ＂ segmented structure. 1. 05 V / 1. 8 V dual supply voltage domain was adopted to ensure DAC＇s perfor-mance. In the DAC,a new data latch working at 1. 05 V /1. 8 V was implemented by combining the latch with the level shifter to simplify the data maintenance pathway. Voltage swing of control signals was reduced by improving the controlling current switch signal generating circuit,so that the output resistance of current source was increased,the clock feedthrough effect was reduced and the dynamic characteristic of DAC was improved. The area of the DAC is 1. 3 mm × 0. 5 mm and the typical power consumption of each channel is 58 m W at differential 150 Ω load. The post-layout simulation results show that spurious free dynamic range（ SFDR） and total harmonic distortion（ THD） of the DAC are 75. 3 d B and- 71. 3 d B respectively,and the integral non-linearity（ INL） is less than 0. 05 LSB and differential non-linearity（ DNL） is less than 0. 08 LSB at 300 MS /s typical sample rate.

关 键 词：数模转换器 电流舵 28 NM 双电压域 锁存 开关控制信号 

分 类 号：TN432[电子电信—微电子学与固体电子学]