一种新型硅片电学测试图形的失效分析方法  

Failure Analysis Method for New Designed Wafer Electrical Test Pattern

作　　者：洪海燕[1] 徐立[1] 周浩[1] 徐海涛[1] Hong Haiyan Xu Li Zhou Hao Xu Haitao(CSMC Technologies Corporation, Wuxi 214028, China)

机构地区：[1]无锡华润上华科技有限公司,江苏无锡214028

出　　处：《半导体技术》2016年第10期794-799,共6页Semiconductor Technology

摘　　要：针对一种新型的多压点复杂硅片电学测试(WET)结构,采用键合技术结合光束导致电阻变化(OBIRCH)缺陷隔离设备,定位芯片异常结构。之后利用扫描电子显微镜(SEM)对平面剥层后的样品进行表面观察,再利用聚焦离子束(FIB)切割仪和透射电子显微镜(TEM)对芯片做进一步的剖面结构物理分析,进而确定导致芯片性能异常的原因。通过手工键合把需要加相同测试条件的金属压点连接在印刷电路板(PCB)或引线框架的同一个电极上,以减少电性能测量时实际所需连接的金属压点的数目,成功确定了特征尺寸为0.11μm的逻辑电路失效产品的两个WET参数失效的根本原因。For a new-designed complicated wafer-electrical-test（ WET） structure with multiple test pins,bonding technique combined with optical beam induced resistance change（ OBIRCH） detects isolation device was used to position the chip abnormal structure. The scanning electron microscope（ SEM）was used to observe the surface of the planar delamination sample. Then the focused ion beams（ FIB）cutting instrument and transmission electron microscope（ TEM） were used to further physically analyze the cross-section structure,thus to confirm the cause of abnormal chip performance. The metal test pins which needed to be added same testing conditions were connected to the printed circuit board（ PCB） or the same electrode of the lead frame by manual bonding to reduce the test pins actually needed in the electrical property measurement. The root cause of two WET parameters failure on the logic circuit product of 0. 11 μm critical dimension was successfully identified.

关 键 词：手动键合 硅片电学测试(WET) 失效分析 缺陷隔离 特征尺寸 

分 类 号：TN407[电子电信—微电子学与固体电子学]