Disordered wall arrays by photo-assisted electrochemical etching in n-type silicon  

作　　者：雷耀虎 赵志刚 郭金川 李冀 牛憨笨 

机构地区：[1]Key Laboratory of Optoelectronic Devices and Systems of Ministry of Education and Guangdong Province, College of Optoelectronic Engineering, Shenzhen University

出　　处：《Journal of Semiconductors》2016年第10期88-92,共5页半导体学报（英文版）

基　　金：Project supported by the National Special Foundation of China for Major Science Instrument (No. 61227802);the National Natural Science Foundation of China (No. 61405120);the National Program on Key Basic Research Project (No. 2012CB825802);the China Postdoctoral Science Foundation (No. 2014M552224)

摘　　要：The fabrication of ordered, high aspect-ratio microstructures in silicon by use of photo-assisted electrochemical etching is an important technology, where voltage and current density are significant factors. In this paper, disordered walls appear in 5-inch n-type silicon wafers when a large current density is used. Based on the theory of space charge region, these disordered walls are caused by the contradiction between the protection from dissolution by a high applied voltage and the dissolution by a high current density. To verify this point, wall arrays were fabricated at different applied voltages and current densities. Moreover, the critical voltage was kept constant and different current densities were applied to obtain conditions for avoiding disordered walls and achieving uniform wall arrays. Finally, a wall array with a period of 5.6 μm and a depth of 55 μm was achieved at an applied voltage of 3 V and a monotonically increasing current density ranging from 22.9 to 24.5 mA/cm^2.The fabrication of ordered, high aspect-ratio microstructures in silicon by use of photo-assisted electrochemical etching is an important technology, where voltage and current density are significant factors. In this paper, disordered walls appear in 5-inch n-type silicon wafers when a large current density is used. Based on the theory of space charge region, these disordered walls are caused by the contradiction between the protection from dissolution by a high applied voltage and the dissolution by a high current density. To verify this point, wall arrays were fabricated at different applied voltages and current densities. Moreover, the critical voltage was kept constant and different current densities were applied to obtain conditions for avoiding disordered walls and achieving uniform wall arrays. Finally, a wall array with a period of 5.6 μm and a depth of 55 μm was achieved at an applied voltage of 3 V and a monotonically increasing current density ranging from 22.9 to 24.5 mA/cm^2.

关 键 词：electrochemical etching wall array high aspect-ratio SILICON disordered wall 

分 类 号：TN305.7[电子电信—物理电子学]