一种采用标准数字单元实现的5bit 100MS/s全数字闪烁型模数转换器  

A 100MS/s 5bit Fully Digital Flash ADC with Standard Cells

作　　者：薛香艳 周雪荣[1] 叶凡[1] 任俊彦[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海201203

出　　处：《复旦学报（自然科学版）》2016年第4期410-417,424,共9页Journal of Fudan University：Natural Science

基　　金：国家科技重大专项(2012ZX03001020)

摘　　要：设计了一种全数字实现的5bit闪烁型模数转换器,该设计的核心思想是通过差分延时链对,将输入的差分模拟信号转换为延时信号,再经过锁存器得到与相应参考电压的比较结果.该数字比较器的参考电压内置于差分延时链对,无需从外部输入.采样保持电路的开关和保持电容也使用数字库中的合适器件代替.该模数转换器完全采用标准数字单元库中的单元搭建而成,与传统实现方法相比,在功耗、面积及设计复杂度上均有了较大程度的改善.电路采用TSMC 65nm工艺设计,核心面积为0.02mm2,在采样频率为100MS/s的情况下,后仿真功耗低达0.6mW,SFDR为37.89dB,ENOB为4.55bit.A fully digital 5 bit Flash ADC is presented here. In this design, differential input analog signals are converted to time delays by a pair of voltage to time converters and the two delay signals are eventually latched to corresponding digit. A series of reference voltages are embedded in a series of voltage to time converter pairs and no reference is needed from the outside. The sample and hold circuit is also implemented with only digital cells. By using standard units from the digital library, this flash ADC is improved a lot in power, area and design complexity compared to conventional analog ADC. This chip is implemented in TSMC 65 nm CMOS technology with the core area of 0. 02 mm2. It consumes as low as 0.6 mW and achieves an SFDR of 37. 89 dB, ENOB of 4. 55 bit under sampling rate of 100 MS/s.

关 键 词：闪烁型模数转换器 全数字模数转换器 内置参考电压 

分 类 号：TN402[电子电信—微电子学与固体电子学]