基于五级流水线的HEVC DBF模块硬件架构设计  

Five-Stage Pipeline Hardware Architecture Design for Deblocking Filter in HEVC

作　　者：沈高峰[1] 陈松[1] 杨晨[1] 杨灿美[2] 

机构地区：[1]中国科学技术大学电子科学与技术系,安徽合肥230027 [2]中国科学技术大学先进技术研究院,安徽合肥230027

出　　处：《微电子学与计算机》2016年第10期1-6,共6页Microelectronics & Computer

摘　　要：DBF(Deblocking Filter)是HEVC解码器中复杂度较高的一个部分,它的处理速度直接影响到整个视频解码器的性能.提出了一种基于五级流水线操作的高性能DBF模块硬件架构,为了消除流水线操作中数据依赖的影响,选取了16×8像素单元作为基本处理单元,占用很少的内部存储器资源.硬件架构使用Verilog硬件描述语言实现,并通过Xilinx-ISE工具进行了电路综合.结果表明,此电路架构能够在48.1 MHz的工作频率下,达到4 096×2 048分辨率60fps高清视频的实时解码要求.Deblocking Filter （DBF） is one of the components which have high computational complexity in HEVC decoder. Its processing speed directly affects the whole performance of video decoders. This paper proposes a high performance five-stage-pipeline-based hardware Architecture of DBF. In order to eliminate the influence of data dependency in the pipeline operation, a 16 × 8 pixels unit is chosen as basic processing unit. This unit occupies very little internal storage resources. The proposed hardware Architecture is implemented in Verilog-HDL. The implementation is synthesized by Xilinx ISE tool. The results show that the proposed architecture can meet requirement of real-time decoding 4 096 × 2 048 @ 60fps high definition video under an operating frequency of 48.1 MHz.

关 键 词：视频编码 HEVC 环路滤波 去方块滤波 硬件架构设计 

分 类 号：TN919.81[电子电信—通信与信息系统]