10GHz扩频时钟发生器的设计  

Design of a 10 GHz Spread Spectrum Clock Generator

作　　者：胡帅帅[1] 周玉梅[1] 张锋[1] 

机构地区：[1]中国科学院微电子研究所,北京100029

出　　处：《微电子学与计算机》2016年第10期63-67,共5页Microelectronics & Computer

基　　金：国家"八六三"高技术研究发展项目(2011AA010403);国家自然科学基金项目(61474134)

摘　　要：扩频时钟是一种减少数字芯片电磁干扰的有效方法.它采用预设好的调制波形,在一定频率范围内对时钟信号进行频率调制.通过小数分频频率综合器和3阶ΔΣ调制器实现了一款10GHz扩频时钟发生器.通过改变多模分频器的分频比来实现扩频的功能.此扩频时钟发生器包括一个传统的锁相环,一个数字3阶MASH 1-1-1ΔΣ调制器和一个波形产生器.扩频时钟发生器产生下扩频5 000×10^(-6)的中心频率为10GHz的信号,调制波形为三角波,调制频率为30.525kHz.本设计已经采用55nm CMOS工艺流片,在1.2V电源电压下的总功耗为20mW.峰值降落为29.3dB,1 MHz频偏处的相位噪声为-110dBc/Hz.Spread spectrum clocking is an effective solution to reduce the electromagnetic interference produced by digital chips, using a clock signal with a frequency that is intentionally swept （frequency modulated） within a certain frequency range, with a predefined modulation profile. A 10 GHz spread spectrum clock generator （SSCG） is realized by a fractional-N frequency synthesizer with a third-order delta-sigma modulator. We accomplish the spread spectrum function by changing the divider ratio. The SSCG integrates a conventional PLL, a digital 3rd order MASH 1-1-1 delta-sigma modulator and an address generator. The SSCG generates clocks at 10 GHz, a 5000 ×10^-6 down spread with a triangular waveform frequency modulation of 30. 525 kHz. This SSCG has been fabricated in a 55nm CMOS process, and it consumes 20 mW from a supply of 1.2 V. The EMI reduction is 29. 3 dB and the simulated phase noise is -110 dBc/Hz at 1 MHz offset.

关 键 词：扩频时钟发生器 锁相环 电磁干扰 ΔΣ调制器 

分 类 号：TN402[电子电信—微电子学与固体电子学]