基于SRIO传输的高速时钟电路的优化设计  

Design Optimization of High—speed Clock Circuit on SRIO transfers

作　　者：杜金艳 叶旭鸣 

机构地区：[1]天津津航计算技术研究所,天津300308

出　　处：《计算机测量与控制》2016年第10期213-214,218,共3页Computer Measurement &Control

摘　　要：针对某信号处理系统在试验、调试的过程中,偶尔出现SRIO链路异常断开的现象进行了深入的分析,发现在SRIO链路工作过程中,链路的高速时钟信号受到了热噪声的影响,引起时钟的过零点采样错误,导致SRIO链路断开;因此,对高速时钟信号的参数进行了分析,提出了增加时钟信号的过渡斜率的优化方案,通过提高锁相环输出的时钟频率,减小了高频噪声,改善了时钟信号过零点的采样的品质;通过试验验证,系统工作稳定可靠,达到了预期效果。To deeply analysis on the SRIO link of a signal which process system can not work properly in the process of testing and de- bugging, we find that Thermal Noise effects for clock signals when the SRIO link work, zero crossing sampling error affects the SRIO link disconnection when the system work. Therefore, thesis discuss the parameter of high speed clock, present solution for an design optimization, by increasing the transition slope of the clock signal, by improving the clock frequency of the output of the phase locked loop, reduce the high frequency noise, improved the quality of the sampling of the zero crossing of the clock signal in the last, the experiment results show that the system works stably and reliably. The proposed method achieves the expected effect.

关 键 词：过零点 热噪声 过渡斜率 可靠 

分 类 号：TP273[自动化与计算机技术—检测技术与自动化装置]