An Encoder with Speed over 40Gbps for RC LDPC Codes with Rates Up to 0.96  

作　　者：HE Zhiyong ZHAO Qiang XU Hushan CUI Wenjuan LUO Yuxi 

机构地区：[1]Institute of Modern Physics, Chinese Academy of Sciences

出　　处：《Chinese Journal of Electronics》2016年第5期921-927,共7页电子学报（英文版）

摘　　要：We propose a class of Rate-compatible(RC) Low-density parity-check(LDPC) codes with a very wide range of code rates. To widen the range of rates, we have developed an optimal transmission scheme to push the upper bound of code rates to 0.96. Characterized by a parity check matrix in a dual-diagonal form, the proposed RC LDPC code can be encoded in linear time. Constructed from shifted identity sub-matrices, the proposed codes are particularly well-suited for the high-speed implementation of parallel encoders. Furthermore, the encoder can be implemented efficiently with several left circular shifters and XOR gates. To maximize the encoding speed, we have proposed a q-parallel encoder architecture, where q is the size of each sub-matrix. The implementation results into Field programmable gate array(FPGA) devices indicate that a72-parallel encoder for the proposed RC LDPC code with a code rate from 0.5 to 0.96 is capable of reaching a speed of 42 Gigabits per second(Gbps) using a clock frequency of 300 MHz.We propose a class of Rate-compatible（RC） Low-density parity-check（LDPC） codes with a very wide range of code rates. To widen the range of rates, we have developed an optimal transmission scheme to push the upper bound of code rates to 0.96. Characterized by a parity check matrix in a dual-diagonal form, the proposed RC LDPC code can be encoded in linear time. Constructed from shifted identity sub-matrices, the proposed codes are particularly well-suited for the high-speed implementation of parallel encoders. Furthermore, the encoder can be implemented efficiently with several left circular shifters and XOR gates. To maximize the encoding speed, we have proposed a q-parallel encoder architecture, where q is the size of each sub-matrix. The implementation results into Field programmable gate array（FPGA） devices indicate that a72-parallel encoder for the proposed RC LDPC code with a code rate from 0.5 to 0.96 is capable of reaching a speed of 42 Gigabits per second（Gbps） using a clock frequency of 300 MHz.

关 键 词：Low-density parity-check codes（LDPC） High-speed encoder Field programmable gate array（FPGA） implementation 

分 类 号：TN911.2[电子电信—通信与信息系统]