ADC evaluation boards design and test framework for LCLS-Ⅱ precision receiver  

作　　者：Jin Yang Gang Huang Qiang Du Lawrence Doolittle John Byrd 

机构地区：[1]Lawrence Berkeley National Laboratory, Berkeley,CA 94720, USA [2]Department of Engineering Physics, Tsinghua University,Beijing 100084, China

出　　处：《Nuclear Science and Techniques》2016年第5期200-207,共8页核技术（英文）

基　　金：supported by the US.Department of Energy(DEAC02-05CH11231);the China Scholarship Council

摘　　要：In the low-level RF control field,ADC acquisition accuracy and noise set the boundary of our control ability,making it important to develop low-noise acquisition systems.From the design to test stage,all the noise terms should be understood and characterized.The specific need addressed here is the precision acquisition system for the second Linac Coherent Light Source(LCLS-Ⅱ),led by SLAC National Accelerator Laboratory.Test circuit boards for the LTC2174 and AD9268 ADCs are designed and fabricated by LBNL.An ADC test framework based on FPGA evaluation board to assess performance has been developed.The ADC test framework includes both DSP(Digital Signal Processing) firmware and processing software.It is useful for low-level RF control and other synchronization projects.Investigating the clock jitter between two channels give us an understanding of that noise source.Working with the test framework,the raw ADC data are transferred to a computer through a Gigabit Ethernet interface.Then short-term error signal can be calculated based on a sine wave fit.By changing low-pass filter bandwidth,relative long-term performance can also be obtained.Amplitude jitter and differential phase jitter are the key issues for ADCs.This paper will report the test results for LTC2174 and AD9268 chips.The integral amplitude jitter is smaller than 0.003%,and the integral phase noise is smaller than 0.0015°(measured at 47 MHz RF,100 MHz clock,bandwidth 1 Hz to 100 kHz) for both ADC chips.In the low- level RF control field, ADC acquisition accuracy and noise set the boundary of our control ability, making it important to develop low-noise acquisition systems. From the design to test stage, all the noise terms should be understood and characterized. The specific need addressed here is the precision acquisition system for the second Linac Coherent Light Source （LCLS-II）, led by SLAC National Accelerator Laboratory. Test circuit boards for the LTC2174 and AD9268 ADCs are designed and fabricated by LBNL. An ADC test framework based on FPGA evaluation board to assess performance has been developed. The ADC test framework includes both DSP （Digital Signal Processing） firmware and processing software. It is useful for low-level RF control and other synchronization projects. Investigating the clock jitter between two channels give us an understanding of that noise source. Working with the test framework, the raw ADC data are transferred to a computer through a Gigabit Ethernet interface. Then short-term error signal can be calculated based on a sine wave fit. By changing low-pass filter bandwidth, relative long-term performance can also be obtained. Amplitude jitter and differential phase jitter are the key issues for ADCs. This paper will report the test results for LTC2174 and AD9268 chips. The integralamplitude j i t te r is smaller than 0.003 %, and the integral phase noise is smaller than 0.0015° （measured at 47 MHz RF, 100 M Hz clock, bandwidth 1 Hz to 100 kHz） fo r both ADC chips.

关 键 词：ADC芯片 测试框架 电路板 设计 评估 接收机 千兆以太网接口 直线加速器 

分 类 号：TP274.2[自动化与计算机技术—检测技术与自动化装置]