基于Vivado HLS的Down Scaler视频系统设计  

Down Scaler Video System Based on Vivado HLS

作　　者：安航[1] An Hang(School of Microelectronics, Xidian University, Xi＇an 710126, China)

机构地区：[1]西安电子科技大学微电子学院,西安710126

出　　处：《单片机与嵌入式系统应用》2016年第11期21-23,共3页Microcontrollers & Embedded Systems

摘　　要：介绍一种基于FPGA的Down Scaler视频系统设计。系统的核心部件采用Xilinx Kintex-7的板载XC7K325T芯片,系统设计使用Vivado工具,包括使用Vivado HLS进行Down Scaler模块设计。首先按照Vivado HLS的代码规范进行Down Scaler模块的C/C++代码编写,然后利用编译工具生成RTL级代码和综合结果 Down Scaler IP核,最后将Down Scaler IP核与TPG、VDMA等Xilinx视频IP核互连,构建实时视频系统。在满足实时性要求和FPGA资源消耗要求的条件下,该设计实现了对Down Scaler视频算法从PC端软件处理方式向FPGA平台硬件处理方式的移植。The design of Down Scaler video system based on FPGA is introduced. The key component of the system is XC7K325T chip on Xilinx Kintex-7 board,and Vivado design suite is used to design,including the use of Vivado HLS for Down Scaler module design. First- ly,the Down Scaler is described with C/C＋＋ language according to the specifications of Vivado HLS. Then,the RTL model and the IP core are generated by the Vivado HLS tool. Finally, a real-time video system is built by connecting the Down Scaler IP core and other Xilinx IP cores such as TPG and VDMA. The design transforms the Down Scaler video algorithm from the PC-based software processing method to the FPGA-based hardware processing method under the condition of meeting the requirementsof real-time performance and FPGA resource consumption.

关 键 词：VIVADO HLS FPGA DOWN SCALER 高层次综合 

分 类 号：TN791[电子电信—电路与系统]