基于FPGA的CRC算法的串行和并行实现  

Serial and parallel implementation of CRC algorithm based on FPGA

作　　者：肖艳艳[1] 何晓雄[1] 

机构地区：[1]合肥工业大学电子科学与应用物理学院,安徽合肥230009

出　　处：《合肥工业大学学报（自然科学版）》2016年第10期1362-1366,共5页Journal of Hefei University of Technology：Natural Science

基　　金：中科院重点实验室开放课题资助项目(IIMDKFJJ-13-06;IIMDKFJJ-14-04)

摘　　要：在数字数据通信系统中,由于信道传输特性不理想以及噪声等干扰,常常会出现一些异常情况。因此,通常在数据通信中添加循环冗余校验(cyclic redundancy check,CRC)码,可以大幅度提高通信的可靠性。文章在论述串行CRC实现的基础上,对电路结构提出了改进的方案,实现了基于现场可编程逻辑门阵列(field programmable gate array,FPGA)的CRC的串行2、4、8位和并行算法,并用超高速集成电路硬件描述语言(very-high-speed integrated circuit hardware description language,VHDL)实现CRC校验,将实验结果下载到DE2,验证了方案的可行性。In digital data communication systems, due to the non-ideal channel transmission characteristics and the noise interference, some abnormal situation often appears in serial communication. Thus, adding the cyclic redundancy check（CRC） check code in the data communication can greatly improve the reliability of communication. On the basis of the analysis of the serial CRC implementation, the improved circuit structure is proposed and the two, four, eight bits serial algorithm and parallel algo- rithm of CRC based on the field programmable gate array（FPGA） are implemented. The CRC check is realized by using the very-high-speed integrated circuit hardware description language（VHDL）, and then the experimental results are downloaded to DE2 to verify the feasibility of the scheme.

关 键 词：循环冗余校验码 串行算法 并行算法 超高速集成电路硬件描述语言 现场可编程逻辑门阵列 

分 类 号：TN919.1[电子电信—通信与信息系统]