基于FPGA的无损图像压缩算法实现  

Implementation of Lossless Image Compression Algorithm Based on FPGA

作　　者：范文晶 王召利 王惠娟 费聚锋 李萧萧 

机构地区：[1]上海机电工程研究所6室,上海201109 [2]上海无线电设备研究所,上海200090

出　　处：《电子科技》2016年第11期126-128,132,共4页Electronic Science and Technology

摘　　要：针对采用传统硬件方法实现JPEG-LS无损图像压缩算法时延时较多、实时性较差的问题,文中提出了一种基于FPGA的全流水线结构来实现JPEG-LS算法。该结构以提高最大吞吐量为主要目标,通过多级流水线降低每一级运算的延迟,大幅提高了压缩算法的实时性,硬件电路操作频率可达120 MHz。The traditional hardware implementation of JPEG-LS lossless image compression algorithm suffers poor real-time performance. This paper presents a fully-pipelined structure based on FPGA to achieve the JPEG-LS algorithm. The structure reduces the delay of every step through Multi-stage pipeline to improve maximum throughput as well as the real-time of the compression algorithm, making hardware circuit operating frequencies up to 120 MHz.

关 键 词：全流水线 无损图像压缩 大吞吐量 FPGA 

分 类 号：TN919.83[电子电信—通信与信息系统] TP391.41[电子电信—信息与通信工程]