任意2^k点存储器结构傅里叶处理器  

Memory-based FFT processor for arbitrary 2^k-point FFTcomputations

作　　者：夏凯锋[1] 周小平[1] 吴斌[1] 

机构地区：[1]中国科学院微电子研究所,北京100029

出　　处：《浙江大学学报（工学版）》2016年第11期2239-2244,共6页Journal of Zhejiang University：Engineering Science

基　　金：国家科技重大专项资助项目(2014ZX03001011-002)

摘　　要：针对任意,点数快速傳里叶变换（FFT）运算,设计并实现一种拥有并行地址无冲突策略的存储器结构FFT处理器.该策略可以支持原位回存,连续帧计算模式,可变多种点数和任意,长度的FFT运算.通过这种地址策略,FFT处理器所能达到的吞吐率由每一级抽取时的限制条件集合个数所决定.因此这种地址策略可以通过改变计算单元基底和调整计算单元并行度的方式可控地调整吞吐率.为了验证本地址策略的可行性,设计一款应用于长期演进（LTE）系统的128-2048点的可配置FFT处理器.处理器采用中芯国际55nmCMOS工艺实现,在122.88MHzX作频率下内核面积为0.615mm^2,功耗为32.4mW.FFT处理器的ASIC结果表明所提策略具有优秀的计算长度灵活性,硬件效率,可以支持任意,长度的FFT计算.An efficient memory-based fast Fourier transform （FFT） processor with parallel conflict-free address scheme was designed for arbitrary 2^k-point FFT computations. The address scheme can support in-place strategy, continuous-flow mode, and variable sizes for arbitrary-long sized FFTs. The available throughput of FFT processor is decided by every stage’s data decimation restriction set number according to this scheme. Then the address scheme can adjust the processor throughput by changing the computation radix and the parallelism of the arithmetic processing units. A configurable 128-2 048 point FFT processor in LTE system was designed to verify the availability of this scheme. The FFT processor occupies 0. 615 mm^2 core area and 32. 4 mW power consumption at 122. 88 MHz frequency in SMIC 55nm technology. The ASIC results show that the proposed address scheme has excellent point flexibility, hardware effi-ciency and can support almost any2^k-point FFT implementations

关 键 词：并行地址无冲突 存连续帧处理 原位回存 存储器结构FFT处理器 

分 类 号：TN47[电子电信—微电子学与固体电子学] TN914.3