一种基于40nm CMOS工艺12位60 MHz流水线模数转换器  

A 12-Bit 60 MHz Pipeline ADC Based on 40 nm CMOS Process

作　　者：谢灿[1,2] 魏子辉[1,2] 黄水龙[1,2] 

机构地区：[1]中国科学院微电子研究所,北京100029 [2]新一代通信射频芯片技术北京市重点实验室,北京100029

出　　处：《微电子学与计算机》2016年第11期54-59,共6页Microelectronics & Computer

基　　金：国家科技重大专项(02)项目(2014ZX02302002)

摘　　要：采用带采样/保持电路,由10级1.5位每级级电路和最后一级为2位flash ADC组成的流水线结构,设计了一种12位60MHz高性能流水线模数转换器.在设计中采用栅压自举开关降低非线性,采用带增益自举的折叠式共源共栅输入级和AB类输出级的运放,采用动态锁存比较器,同时逐级优化级电路中采样电容以及运放的增益和带宽.在SMIC 40nm CMOS工艺下,当输入信号为1.875 MHz,采样速率为60 MHz时,SNDR为68.7dB,SFDR为74.6dB,ENOB为11.12bit,芯片的核心面积为0.95mm2,1.1V的电源电压下,消耗的总电流为56mA.A 12-bit 60 MHz high-performance pipeline ADC is designed in this paper, which consists of sample/hold circuit, 1. 5-bit/stage conversion circuit applied from lst to 10th and a 2-bit flash ADC of the last stage. In this design a gate-bootstrapping switch was used to reduce nonlinear, an operational amplifier with a gain-boosting folded cascade input stage and a class AB output stage was used, dynarnie latch eomparator was used too, meanwhile, optimizing the sampling capacitor, the gain and bandwidth of the operational amplifier in the circuit stage by stage. In a SMIC 40 nm CMOS process, when the input signal frequency was 1. 875 MHz and the sampling frequency was 60 MHz, the SNDR was 68. 7 dB, the SFDR was 74. 6 dB, the ENOB was 11.12 bits, the core area of chip was 0. 95 mm2 , the total dissipation current was 56 mA under the 1.1 V supply voltage.

关 键 词：流水线模数转换器 高性能 采样/保持电路 栅压自举开关 动态锁存比较器 

分 类 号：TN4[电子电信—微电子学与固体电子学]