基于电流源拆分均衡布局的14 bit 200 MS/s电流舵DAC设计  

Design of 14-bit 200 MS/s Current-Steering DAC Based on Split and Symmetricalal Layout of Current Sources

作　　者：戴澜[1] 江礼阳 韩小娟[2] 

机构地区：[1]北方工业大学电子信息工程学院微电子系,北京100144 [2]渤海石油职业学院,河北任丘062550

出　　处：《微电子学与计算机》2016年第11期60-63,共4页Microelectronics & Computer

摘　　要：对一种高性能的14bit 200 MHz电流舵型数模转换器进行设计.对电流舵DAC主要误差进行分析建模,并以此为依据结合工艺特性计算电流源单元晶体管大小;采用一种新型限幅电路减少输出毛刺;对输出电流源单元和开关阵列采用Q^2 Random Walk布局减少工艺误差,最后采用SMIC 0.18μm混合CMOS工艺对芯片进行实现.采用3.3V/1.8V供电,输入信号频率为1 MHz和20 MHz,采样频率为200 MHz时,SFDR后仿真结果分别为100.1dB,88.3dB.In this paper it proposes a high performance 14-bit 200 Ms/s current-steering DAC. It analyses the non- ideal factors and models the proposal DAC based on Verilog-A, adopts a swing limited circuit to process the control signal of current source switches, and introduces a split and symmetrical layout of current sources scheme to reduce the process error in fabrication. At last, it is fabricated with SMIC 0. 18μm Mixed-Signal CMOS technology. With 3.3 V/1.8 V power supply, the SFDR in the post simulation results of this DAC are 100. 1 dB and 88. 3 dB respectively under the condition of 1 MHz and 20 MHz input signal and 200 MHz sample clock.

关 键 词：数模转换器 毛刺 时钟馈通 电流源阵列 

分 类 号：TN4[电子电信—微电子学与固体电子学]