一种双门限语音端点检测算法的ASIC实现  

A Double Threshold Speech Endpoint Detection Algorithm Implementation in ASIC

作　　者：张羊[1] 姜汉钧[1] 王志华[1] 

机构地区：[1]清华大学微电子所,北京100084

出　　处：《微电子学与计算机》2016年第11期69-73,共5页Microelectronics & Computer

摘　　要：设计了一种基于短时幅度和过零率双门限判决算法的语音端点检测ASIC实现电路,采用基于异步FIFO的动态分帧和CSD编码技术大大节省了硬件资源开销,在Modelsim和FPGA上分别进行了采集的语音信号的检测验证,结果表明此算法具有硬件实现简单、资源消耗小、检测正确率高的优点.A kind of speech endpoint detection ASIC circuit is designed, which is based on double threshold detection algorithm of short-term magnitude and zero-crossing rate. We can greatly save the cost of hardware resourcesby usingdynamic frame partition technology based on asynchronous FIFO and CSD coding technology. We have completed the verification using the collected speech signal in Modelsim and FPGA platform respectively. The results show that this algorithm has the advantages of simple hardware implementation, low resource consumption and high detection accuracy.

关 键 词：双门限 语音端点检测 ASIC FIFO CSD FPGA 

分 类 号：TN492[电子电信—微电子学与固体电子学]