一种12位4MS/s异步SAR ADC  

A 12-Bit 4MS/s Asynchronous SAR ADC

作　　者：李彬[1,2] 周梦嵘 谢亮[1,2] 金湘亮[1,2] 

机构地区：[1]湘潭大学物理与光电工程学院,湖南湘潭411105 [2]微光电与系统集成湖南省工程实验室,湖南湘潭411105

出　　处：《微电子学》2016年第5期590-594,共5页Microelectronics

基　　金：国家自然科学基金资助项目(61274043);国家自然科学基金重点项目(61233010);湖南省自然科学杰出青年基金资助项目(2015JJ1014)

摘　　要：设计了一种12位4MS/s的异步逐次逼近型模数转换器(SAR ADC)。采用一种既能节省开关动态功耗又能减小电容面积的开关切换策略,与传统结构相比,开关动态切换功耗节省了95%,电容总面积减小了75%。为了避免使用高频时钟,采用了异步控制逻辑,采样开关采用栅压自举开关以便提高ADC的线性度,动态锁存比较器的使用减小了静态功耗,片上集成了电压参考电路和相关驱动电路。基于SMIC 0.18μm CMOS工艺,在1.8V电源电压和4 MS/s转换速率条件下,经后仿真得到ADC的信号噪声失真比SNDR为70.2dB,功耗仅为0.9 mW,品质因素FOM为109fJ/conversion-step。A 12-bit 4MS/s successive approximation register（SAR）analog-to-digital converter（ADC）using an energy-and area-efficient switching procedure was presented.The proposed ADC could save 95% switching energy and achieve a 4× reduction in total capacitance＇s area in comparison with the conventional SAR ADC.The ADC used an asynchronous control logic to avoid the use of high frequency clock,and a dynamic latch comparator was used to minimize the quiescent power dissipation.Gate voltage bootstrapped switch was used to improve the ADC＇s linearity.An integrated voltage reference and a buffer were employed.The proposed ADC had been simulated in the SMIC 0.18μm CMOS technology.The post simulation results showed that,the ADC achieved a SNDR of 70.2dB while dissipating 0.9mW and resulting in a figure-of-merit（FOM）of 109fJ/conversion-step at a 1.8-V supply and4 MS/s.

关 键 词：逐次逼近型 模数转换器 异步 

分 类 号：TN432[电子电信—微电子学与固体电子学] TN792