一种5Gb/s双信道并行时钟数据恢复电路  

A 5Gb/s 2-Channel Parallel Clock and Data Recovery Circuit

作　　者：李志贞[1] 张长春[1,2] 高罗丝[1] 赵江[1] 宋韦 郭宇锋[1,2] 

机构地区：[1]南京邮电大学电子科学与工程学院,南京210003 [2]南京邮电大学江苏省射频集成与微组装工程实验室,南京210003

出　　处：《微电子学》2016年第5期599-604,共6页Microelectronics

基　　金：江苏省自然科学基金资助项目(BK20130878;BK2012435;BK20141431);江苏省普通高校研究生科研创新计划资助项目(SJLX_0374;SJLX_0375);江苏省科技支撑项目工业部分(BE2013130);高等教育博士点基金资助项目(20133223120005;20133223110003)

摘　　要：基于0.18μm CMOS工艺,设计了一种双信道并行时钟数据恢复(CDR)电路,它由1个锁相环(PLL)型CDR和1个相位选择/相位插值(PS/PI)型CDR结合实现。与传统的并行CDR相比,该CDR电路不需要本地参考时钟。PLL型CDR中环形压控振荡器的延迟单元采用电感峰化技术,拓展了带宽,实现了较高的振荡频率;电荷泵采用自举基准和运放,改善了充放电电流匹配。PS/PI型CDR中Bang-Bang型鉴相器结构简单,具有较好的鉴相功能;PS/PI电路比传统结构少2个相位选择器。仿真结果表明,当输入并行数据速率为5Gb/s时,恢复出的2组时钟与数据的峰峰抖动值分别为6.1ps,8.1ps和8.7ps,11.2ps。电路核心模块的功耗为172.4mW,整体电路版图面积为(1.7×1.585)mm^2。Based on a 0.18μm CMOS process,a 5Gb/s/ch 2-channel parallel CDR was proposed,which was realized by a PLL-based CDR and a phase selection/phase interpolation（PS/PI）-based CDR.In comparison with the conventional circuits,the proposed circuit didn＇t need local reference clock.In the PLL-based CDR,the inductive shunt peaking technique was proposed to expand the bandwidth of the delay cell of the VCO.The bootstrap references and op amps were used to improve the charging-and-discharging current matching.In the PS/PI-based CDR,the Bang-Bang PD had a good function,and its structure was simple.Two PS were eliminated in the PS/PI circuit in comparison with the conventional circuits.The simulation results showed that the peak-to-peak jitters of the recovered clocks were 6.1ps and 8.1ps respectively for 2parallel PRBS input data and the peak-to-peak jitters of the two recovered data were 8.7ps and 11.2ps respectively.The core power consumption was 172.4mW and the whole die area was（1.7×1.585）mm^2.

关 键 词：并行时钟数据恢复 锁相环 相位选择 相位插值 

分 类 号：TN453[电子电信—微电子学与固体电子学]