高速电路设计中过孔对信号完整性影响的研究  

Effects of Via on Signal Integrity in High-speed Circuit Design

作　　者：胡佳栋 李诚[1,2] 曹喆 刘树彬[1,2] 安琪[1,2] 

机构地区：[1]核探测与核电子学国家重点实验室,中国科学技术大学,合肥230026 [2]中国科学技术大学近代物理系,合肥230026

出　　处：《核电子学与探测技术》2016年第6期596-601,共6页Nuclear Electronics & Detection Technology

基　　金：安徽省自然科学基金(1608085QA21);国家自然科学基金(11505182)资助

摘　　要：随着信号的频率越来越高,高速电路设计中过孔对信号完整性的影响越来越不可忽视,实测带过孔的PCB走线的S参数发现过孔对系统信号完整性有比较大的影响。通过ANSYS仿真软件及理论计算对此进行了研究,发现过孔对信号完整性的影响主要源于两方面:过孔的寄生参数和内电层平面的谐振。减少信号走线中过孔的使用、调整过孔的位置以及消除谐振能有效改进高速电路的信号完整性。论文通过ANSYS仿真以及PCB实测验证了这些方法的有效性。该结论对高速电路设计有参考意义。As signal frequency increases, the effects of via on signal integrity become more and more significant in high - speed circuit design. S - parameters testing of PCB traces with vias found that vias have a great impact on the system signal integrity. ANSYS software simulation reveals that the effects of via on signal integrity come from the parasitic parameters of vias and the resonance of inner layer planes. Therefore, reducing vias of signal traces, adjusting position of vias and eliminating resonance can significantly improve the system signal integrity. Then this article verifies the effectiveness of these methods by ANSYS software simulation and PCB test. This conclusion has reference to high - speed circuit design.

关 键 词：PCB过孔 内电层谐振 高速电路设计 信号完整性 

分 类 号：TN710[电子电信—电路与系统]