基于FPGA中状态机的逻辑等价性验证方法  

Logic Equivalence Checking Based on the State Machine in FPGA

作　　者：朱倩[1,2] 田甜[1,2] 赵欢[1,2] 

机构地区：[1]北京控制工程研究所,北京100190 [2]北京轩宇信息技术有限公司,北京100190

出　　处：《南通大学学报（自然科学版）》2016年第3期45-49,共5页Journal of Nantong University(Natural Science Edition)　

摘　　要：采用Synopsys公司的逻辑等价性验证工具Formality,针对状态机逻辑电路进行逻辑等价性验证.介绍了验证的基本流程和具体步骤,具体分析了在逻辑等价性验证过程中出现的由安全设置、状态机耦合性和广义状态机等引发的常见状态机验证失败问题,并最终提出有效、可靠的解决方案.结果表明,采用Formality针对大型复杂的FPGA状态机进行逻辑等价性验证,能大幅度降低验证周期,提高验证正确性,从而进一步提高航天产业背景下FPGA产品的可靠性.In the context of Synopsys′s logical equivalence checking tool Formality, the basic processes and specific steps of logic equivalence checking in the state machine during actual FPGA verification process was introduced. And the common verification problems triggered by safe attribute, coupling between state machines and the general state machine were also explored to present effective and reliable solutions. The results revealed that it could reduce the verification period, and improve the accuracy of verification. Moreover, it could improve the reliability of FPGA products under the backgroud of aerospace industry. This article has carried on correlative research and has finally put forward some effective and reliable solutions.

关 键 词：FPGA验证 状态机 逻辑等价性 

分 类 号：TN492[电子电信—微电子学与固体电子学]