异步信号的同步化逻辑时序及电路结构研究  

Research on synchronous logic sequence and circuit structure of asynchronous signals

作　　者：刘海成[1] 邹海英[1] 佟宁宁[1] 

机构地区：[1]黑龙江工程学院电气与信息工程学院,黑龙江哈尔滨150050

出　　处：《黑龙江工程学院学报》2016年第5期38-42,共5页Journal of Heilongjiang Institute of Technology

基　　金：黑龙江省教育厅科学技术研究项目(12541673)

摘　　要：为实现异步信号接入同步时序逻辑电路,则需要通过异步信号的同步化电路将异步信号转换为可同步的时序,包括异步信号的采样、"准稳态"问题和异步信号的自动撤销等3个问题。文中给出了解决该问题的电路结构组成、3种同步化时序和5种具体的实现电路,为基于FPGA进行复杂系统设计提供异步信号解决方案。实际测试表明,系统具有稳定性好和结构简单等特点。T he realization of asynchronous signals accessed by synchronized sequential logic circuits ,needs asynchronous signal conversion for synchronization timing through the synchronization circuit of asynchronous signal , including three parts ： asynchronous signal sampling , “quasi steady” and asynchronous signal automatic revocation . T his paper gives a circuit structure , three kinds of synchronization time series and five kinds of realization circuit to provide asynchronous signal solution for complex system design based on FPGA .The tests show this system servers stable and simplified in its structure .

关 键 词：异步信号 同步化 时序 电路 

分 类 号：TM131.5[电气工程—电工理论与新技术]