基于芯核分层布图的3D芯片扫描链优化设计  

Optimal design of 3D chip scan chains based on cores-hierarchical-placement

作　　者：王伟[1,2] 朱侠[1,2] 方芳[1] 秦振陆[1,2] 郭二辉 任福继[1,2] 

机构地区：[1]合肥工业大学计算机与信息学院,合肥230009 [2]合肥工业大学情感计算与先进智能机器安徽省重点实验室,合肥230009 [3]中国电子科技集团第三十八研究所,合肥230009

出　　处：《电子测量与仪器学报》2016年第10期1482-1489,共8页Journal of Electronic Measurement and Instrumentation

基　　金：国家自然科学基金重点项目(61432004);国家自然科学基金(61474035;61204046;61306049);安徽省科技攻关项目(1206c0805039);安徽省自然科学基金(1508085QF129);教育部新教师基金(20130111120030)资助项目

摘　　要：随着3D堆叠技术的不断发展,芯片测试已成为一大研究热点。为了减少三维堆叠集成电路(three dimensional stacked integrated circuits,3D-SICs)绑定前和绑定中的总测试时间,提出了基于芯核分层布图的改进模拟退火算法和扫描链分配算法,通过将芯核均匀地分配到各层上实现对各层电路中芯核合理化地布图,再利用"绑定中测试"复用"绑定前测试"扫描链的方式,协同优化绑定前和绑定中的总测试时间和硬件开销。在ITC’02基准电路上的实验结果表明,本文方法在TSV数量的约束下,测试时间和硬件开销分别最高降低了27.26%和89.70%,且各层芯核布图更加均匀。Test of 3D-SICs based on cores has already become the bottleneck for the development of 3D stacked technology. A new cores allocation algorithm which is called improved simulated annealing algorithm based on cores-hierarchical-placement is proposed to distribute cores evenly to each layer to get a more reasonable arrangement. And then a scan chains allocation algorithm, in which the mid-bond test reutilizes the scan chains in the pre-bond test, is proposed to minimize the overall test time and the hardware overhead. The experimental results on ITC＇02 test benchmarks show that by co-optimizing the overall test time and the hardware overhead for the pre-bond test and the mid-bond test can reduce the test time and the hardware overhead up to 27.26% and 89. 70% under the constraints of the TSVs, respectively. Besides, the placement of the cores for each layer is more homogeneous.

关 键 词：芯核分层布图 绑定前测试 绑定中测试 协同优化 扫描链均衡 硬件开销 

分 类 号：TN405[电子电信—微电子学与固体电子学]