一种采用单双跳变的低功耗确定性BIST方案  

Low power deterministic BIST based on SDIC

作　　者：张建伟[1] 丁秋红[1] 周彬[2] 滕飞[1] 马万里[1] 王政操 陈晓明[1] 李志远[3] 

机构地区：[1]大连理工大学电子科学与技术学院,辽宁大连116024 [2]哈尔滨工业大学空间基础科学研究中心,哈尔滨150001 [3]黑龙江大学电子工程学院,哈尔滨150080

出　　处：《哈尔滨工业大学学报》2016年第11期96-102,共7页Journal of Harbin Institute of Technology

基　　金：国家自然科学基金(61306091;61100031;61340050;61204132);中央高校基本科研业务费专项资金资助(DUT15QT46);黑龙江省高校重点实验室开放课题

摘　　要：为实现低功耗和高故障覆盖率,基于单跳变测试技术和2-bit扭环计数器,提出一种新型的单双跳变的确定性测试向量产生器.首先,与一般的确定性测试方案直接存储确定性种子不同,利用ROM存储控制信号并通过单双跳变生成确定性种子和确定性测试向量,这样控制信号的长度约为确定性种子的1/2,有利于降低功耗并节约存储空间.其次,2-bit减法计数器合理地过滤了冗余向量,大大缩短了测试时间并降低总体能耗.最后,为了适应不同的测试需求,还设计了相应的测试向量压缩算法和三种x指定算法.实验结果表明,平均功耗分别降低了42.36%、32.32%、38.94%,测试长度分别减少了77.6%、86.1%、84.3%,测试数据分别压缩了79.4%、65.2%、68.1%.In order to obtain low power consumption and high fault coverage,a new single-double input change deterministic test pattern generator is presented based on a single input change technology and 2-bit twisted ring counter. Firstly,unlike traditional deterministic test schemes storing the deterministic seeds,the presented scheme saves the control signal bits in ROM. With these bits,the deterministic seeds and patterns are generated by singledouble input change. It is beneficial for power consumption and area overhead because the length of control signal bits are just about 1/2 of deterministic seed ＇s. Secondly,2-bit down counter can reasonably filter redundant vector,and it greatly shorten test time and reduce overall energy consumption. At last,considering different needs,the test pattern compression algorithm and three kinds of x assignment algorithm are proposed. Experimental results show that the average power reductions are up to 42.36%,32.32%,38.94%,and the test length reductions are up to77.6%,86.1%,84.3%,and then the test data storages are decreased by 79.4%,65.2%,68.1%,respectively.

关 键 词：扭环计数器 低功耗 确定性 测试向量生成器 单跳变 

分 类 号：TN791[电子电信—电路与系统]