一种使用BU-65170内部RAM实现双缓冲的星载1553B总线数据传输技术  

A 1553B Bus Data Transmission Technology Using BU-65170 Internal RAM for Double-buffer on Payload

作　　者：蔡跃荣[1,2,3] 朱光武[1,3] 孙越强[1,3] 杜起飞[1,3] 王先毅[1,3] 王冬伟[1,3] 吴迪[1,3] 吴春俊[1,3] 白伟华[1,3] 孟祥广[1,3] 柳聪亮[1,3] 李伟 刘成[1,3] 夏俊明[1,3] CAI Yue-rong ZHU Guang-wu SUN Yue-qiang DU Qi-fei WANG Xian-yi WANG Dong-wei WU Di WU Chun-jun BAI Wei-hua MENG Xiang-guang LIU Cong-liang LI Wei LIU Cheng XIAJun-ming(National Space Science Center, Chinese Academy of Sciences1 , Beijing 100190, P. R. China University of Chinese Academy of Sciences, Beijing 100049, P. R. China Beijing Key Laboratory of Space Environment Exploration , Beijing 100190, P. R. China)

机构地区：[1]中国科学院国家空间科学中心,北京100190 [2]中国科学院大学,北京100049 [3]天基空间环境探测北京市重点实验室,北京100190

出　　处：《科学技术与工程》2016年第31期41-45,共5页Science Technology and Engineering

摘　　要：星载1553B总线数据传输通常需要使用外部RAM缓存待发送数据,使用外部RAM带来系统功耗和面积的增加,也增加了系统的复杂性。提出了一种使用1553B芯片内部RAM实现双缓冲的数据传输方案。此方案采用FPGA作为主控芯片,BU-65170作为1553B总线控制芯片,利用BU-65170内部RAM的两个地址空间段构成双缓冲,避免使用外部RAM,简化了系统硬件设计,提高了系统的可靠性。对双缓冲区采取交替更新访问方式,实现了1553B总线数据的可靠传输。此方案已成功应用于星载GNOS掩星探测仪。Generally an external RAM is used to cache data to be sent by 1553B bus on payloads, but using ex- ternal RAM will increase system power consumer and area, as well to system complexity. A data transmission scheme using 1553B chip internal RAM for double-buffer is proposed. FPGA is the core control unit, and BU- 65170 is the control chip of 1553B bus. To simplify hardware design, not external RAM, but two different spaces in BU-65170 internal RAM are used for double-buffer, updated and accessed in return, to achieve 1553B bus data transmission reliably. The scheme has been successfully applied to the payload of GNOS occultation Detector.

关 键 词：FPGA 1553B 双缓冲 

分 类 号：TN919.3[电子电信—通信与信息系统]