HEVC中CABAC解码器的硬件设计与实现  

Hardware design and implementation of CABAC decoder in HEVC

作　　者：袁星范 蔡敏[1] 

机构地区：[1]华南理工大学电子与信息学院,广东广州510640

出　　处：《电子设计工程》2016年第22期57-59,63,共4页Electronic Design Engineering

摘　　要：基于上下文自适应二进制算术编码(CABAC)是HEVC中采用的一种高效熵编码,具有很高的压缩比,但实现结构复杂,且很难并行化。本文设计了一个高性能的CABAC解码器,并对单周期解码1bit的硬件结构进行了优化,同时采用流水线结构,进一步提高了解码性能。采用0.18μm CMOS工艺,综合后面积为48K个逻辑门,工作频率为250 MHz,解码速度达到1 bit/cycle,适用于高清视频领域。context based adaptive binary arithmetic encoding（CABAC） is a kind of high efficient entropy encoding used in HEVC, which has a high compression ratio, but it is complex and difficult to be parallel. In this paper, a high performance CABAC decoder is designed, and the hardware structure of the single cycle decoding lbit is optimized, and the pipeline structure is used to improve the decoding performance. With the 0.18μm CMOS process, the integrated area is 97K logic gates, the working frequency is 250MHz, the decoding speed reaches lbit/cycle, which is suitable for the field of HD video.

关 键 词：CABAC HEVC 二进制算术编码 硬件设计 

分 类 号：TN4[电子电信—微电子学与固体电子学]