Low Cost 1D DCT Core for Multiple Video Codec  

作　　者：JIA Rui CHEN Rui LIN Colin Yu GUO Zhenhong YANG Haigang 

机构地区：[1]Institute of Electronics,Chinese Academy of Sciences,Beijing 100190,China [2]The University of Chinese Academy of Sciences,Beijing 100190,China

出　　处：《Chinese Journal of Electronics》2016年第6期1052-1057,共6页电子学报（英文版）

基　　金：supported by the National Natural Science Foundation of China(No.61271149,No.61106033,No.61204045)

摘　　要：The expandability of high demands for multimedia applications brings out more and more video standards for improving the coding and compression efficiency. As the most commonly used transform, Discrete cosine transform(DCT) achieves excellent energy compaction property and good compression efficiency. Hardware sharing is the mostly used efficient strategy to reduce the cost for video codec. Based on traditional matrix factorization, this paper makes three observations to direct the design of proposed hardware sharing architecture. The proposed architecture can be generally used to compute 8×8 DCT of AVS, H.264, VC-1 and HEVC in a low cost way, and can be used to decode Full-HD and WQXGA formate video sequences in real time. The design has been synthesized in 0.13μm technology. The synthesis results show that the proposed architecture achieves76.9% reduction in gate count, 85.6% decrease in power consumption and 35% improvement in operational speed in comparison with other existing designs.The expandability of high demands for multimedia applications brings out more and more video standards for improving the coding and compression efficiency. As the most commonly used transform, Discrete cosine transform（DCT） achieves excellent energy compaction property and good compression efficiency. Hardware sharing is the mostly used efficient strategy to reduce the cost for video codec. Based on traditional matrix factorization, this paper makes three observations to direct the design of proposed hardware sharing architecture. The proposed architecture can be generally used to compute 8×8 DCT of AVS, H.264, VC-1 and HEVC in a low cost way, and can be used to decode Full-HD and WQXGA formate video sequences in real time. The design has been synthesized in 0.13μm technology. The synthesis results show that the proposed architecture achieves76.9% reduction in gate count, 85.6% decrease in power consumption and 35% improvement in operational speed in comparison with other existing designs.

关 键 词：Discrete cosine transform（DCT） 8×8 integer transform AVS H.264 VC-1 HEVC Hardware sharing 

分 类 号：TN919.81[电子电信—通信与信息系统]