Configurable Floating-Point FFT Accelerator on FPGA Based Multiple-Rotation CORDIC  

作　　者：CHEN Jiyang LEI Yuanwu PENG Yuanxi HE Tingting DENG Ziye 

机构地区：[1]College of Computer,National University of Defense and Technology (NUDT)

出　　处：《Chinese Journal of Electronics》2016年第6期1063-1070,共8页电子学报（英文版）

基　　金：supported by Aerospace Science Fund of China(No.2013ZC88003);the National Natural Science Foundation of China(No.61402499)

摘　　要：Fast Fourier transform(FFT) accelerator and Coordinate rotation digital computer(CORDIC) algorithm play important roles in signal processing. We propose a configurable floating-point FFT accelerator based on CORDIC rotation, in which twiddle direction prediction is presented to reduce hardware cost and twiddle angles are generated in real time to save memory. To finish CORDIC rotation efficiently, a novel approach in which segmentedparallel iteration and compress iteration based on CSA are presented and redundant CORDIC is used to reduce the latency of each iteration. To prove the efficiency of our FFT accelerator, four FFT accelerators are prototyped into a FPGA chip to perform a batch-FFT. Experimental results show that our structure, which is composed of four butterfly units and finishes FFT with the size ranging from 64 to8192 points, occupies 33230(3%) REGs and 143006(30%)LUTs. The clock frequency can reach 122 MHz. The resources of double-precision FFT is only about 2.5 times of single-precision while the theoretical value is 4. What's more, only 13331 cycles are required to implement 8192-points double-precision FFT with four butterfly units in parallel.Fast Fourier transform（FFT） accelerator and Coordinate rotation digital computer（CORDIC） algorithm play important roles in signal processing. We propose a configurable floating-point FFT accelerator based on CORDIC rotation, in which twiddle direction prediction is presented to reduce hardware cost and twiddle angles are generated in real time to save memory. To finish CORDIC rotation efficiently, a novel approach in which segmentedparallel iteration and compress iteration based on CSA are presented and redundant CORDIC is used to reduce the latency of each iteration. To prove the efficiency of our FFT accelerator, four FFT accelerators are prototyped into a FPGA chip to perform a batch-FFT. Experimental results show that our structure, which is composed of four butterfly units and finishes FFT with the size ranging from 64 to8192 points, occupies 33230（3%） REGs and 143006（30%）LUTs. The clock frequency can reach 122 MHz. The resources of double-precision FFT is only about 2.5 times of single-precision while the theoretical value is 4. What＇s more, only 13331 cycles are required to implement 8192-points double-precision FFT with four butterfly units in parallel.

关 键 词：Fast Fourier transform（FFT） Coordinate rotation digital computer（CORDIC） FPGA Floating-point 

分 类 号：TN791[电子电信—电路与系统] TP332[自动化与计算机技术—计算机系统结构]