基于JESD204B接口协议的组帧器电路设计  

Implementation of the Framer Circult of JESD204B Interface Protocol

作　　者：陶加祥[1] 王巍[1] 霍兴华[1] 姚亚峰[1] 

机构地区：[1]中国地质大学机械与电子信息学院,武汉430074

出　　处：《电子技术（上海）》2016年第10期58-61,共4页Electronic Technology

基　　金：湖北省自然科学基金面上项目(2014CFB896)资助课题

摘　　要：随着数模转换器的转换速率越来越高,JESD204B串行接口逐渐成为芯片间数据传输的主流接口。在深入理解JESD204B协议中有关M、S、L、F参数规定和组帧原理的基础上,采用三级映射结构实现了一种通用的四字节组帧电路设计。该电路由于采用分级映射方法,方便实现JESD204B协议所规范的各种组帧模式,并通过采用四字节并行处理技术,降低了电路对系统时钟的要求,适合低成本CMOS工艺实现。电路综合结果表明,该组帧器符合JESD204B协议规定的性能指标要求,可应用于JESD204B串行接口电路的自主设计。With the DAC＇s conversion rate increasing, JESD204 B serial interface is becoming the mainstream for the data transaction between chips. Based on the in-depth understanding of the M, S, L, F parameter specification and the framing principle in JESD204 B, A three-level map structure is proposed to achieve a widely applicable quad-byte framer circuit design. The hierarchical mapping method is facilitate to the realization of various of different framing mode specified in JESD204 B protocol, also by using a quad-byte parallel processing technology to reduce the system clock requirements and make it facilitate to implementation with low-cost CMOS technology. The simulation results show that the design fully meets the performance requirements of JESD204 B protocol and can be applied to the independent design of JESD204 B serial interface.

关 键 词：JESD204B Serdes接口 组帧器 并行处理技术 

分 类 号：TN919.3[电子电信—通信与信息系统]